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products and specifications discussed herein ar e subject to change by micron without notice. 4gb: x4, x8 twindie ddr3 sdram functionality pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 1 ?2008 micron technology, inc. all rights reserved. twindie tm ddr3 sdram mt41j1g4 ? 64 meg x 4 x 8 banks x 2 ranks mt41j512m8 ? 32 meg x 8 x 8 banks x 2 ranks for component data sheets, refer to micron?s web site: www.micron.com functionality the 4gb twindie ? ddr3 sdram uses micron?s 2gb ddr3 die and has similar functionality. this data sheet includes key timing parameters, ball assignments, a functional description, fu nctional block diagrams, idd specifications, and package dimensions. refer to micron?s 2gb ddr3 sdram data sheet for complete specifications. (specifications for base part number mt41j512m4 correlate to tw indie manufacturing part number mt41j1g4; specificat ions for base part num- ber mt41j256m8 correlate to twindie manufacturing part number mt41j512m8.) features ? uses 2gb micron die ? two ranks (includes dual cs#, odt, cke, and zq balls) ? each rank has 8 internal banks ?v dd = v ddq = +1.5v 0.075v ? 1.5v center-terminated push/pull i/o ? jedec-standard ball-out ?low-profile package ?t c of 0c to 95c ? 0c to 85c: 8192 refresh cycles in 64ms ? 85c to 95c: 8192 refresh cycles in 32ms notes: 1. cl = cas (read) latency. options marking ? configuration ? 64 meg x 4 x 8 banks x 2 ranks 1g4 ? 32 meg x 8 x 8 banks x 2 ranks 512m8 ? fbga package (lead-free) ? 82-ball fbga (12.5 x 15 x 1.35mm) rev. a thu ? 78-ball fbga (9 x 11.5 x 1.2mm) rev. d thd ? timing ? cycle time 1 ? 1.5ns @ cl = 10 (ddr3-1333) -15 ? 1.5ns @ cl = 9 (ddr3-1333) -15e ? 1.87ns @ cl = 8 (ddr3-1066) -187 ? 1.87ns @ cl = 7 (ddr3-1066) -187e ? 2.5ns @ cl = 6 (ddr3-800) -25 ? 2.5ns @ cl = 5 (ddr3-800) -25e ? self refresh ? standard none ? operating temperature ? commercial (0c t c 95c ) none ? revision (82-ball fbga) :a ? revision (78-ball fbga) :d table 1: key timing parameters speed grade data rate (mt/s) target t rcd- t rp-cl t rcd (ns) t rp (ns) cl (ns) -15 1333 10-10-10 15 15 15 -15e 1333 9-9-9 13.5 13.5 13.5 -187 1066 8-8-8 15 15 15 -187e 1066 7-7-7 13.1 13.1 13.1 -25 800 6-6-6 15 15 15 -25e 800 5-5-5 12.5 12.5 12.5
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 2 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram features table 2: addressing parameter 1024 meg x 4 512 meg x 8 configuration 64 meg x 4 x 8 banks x 2 ranks 32 meg x 8 x 8 banks x 2 ranks refresh count 8k 8k row address 32k a[14:0] 32k a[14:0] bank address 8 ba[2:0] 8 ba[2:0] column address 2k a[11, 9:0] 1k a[9:0]
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 3 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram ball assignments and descriptions ball assignments and descriptions figure 1: 82-ball fbga ball assignments ? rev. a (top view) notes: 1. balls with black dots are increm ental to balls on the monolithic die. 6 7 5 3 v dd v ss q dq2 nf, dq 6 v ddq v ss v dd cs 0# ba0 a3 a5 a7 re s et# 4 n c dq0 dq s dq s # nf, dq4 ra s # c a s # we# ba2 a0 a2 a9 a13 8 nf, nf/tdq s # dm, dm/tdq s dq1 v dd nf, dq7 c k c k# a10/ap n c a12/b c # a1 a11 a14 9 v ss v ss q dq3 v ss nf, dq5 v ss v dd zq0 v ref c a ba1 a4 a 6 a8 10 v dd v ddq v ss q v ss q v ddq c ke1 c ke0 zq1 v ss v dd v ss v dd v ss 2 v ss v ss v ddq v ss q v refdq odt1 odt0 cs 1# v ss v dd v ss v dd v ss 1 n c n c 11 n c n c a b c d e f g h j k l m n
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 4 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram ball assignments and descriptions figure 2: 78-ball fbga ball assignments ? rev. d (top view) 5 6 4 2 v dd v ss q dq2 nf, dq 6 v ddq v ss v dd cs 0# ba0 a3 a5 a7 re s et# 3 n c dq0 dq s dq s # nf, dq4 ra s # c a s # we# ba2 a0 a2 a9 a13 7 nf, nf/tdq s # dm, dm/tdq s dq1 v dd nf, dq7 c k c k# a10/ap n c a12/b c # a1 a11 a14 8 v ss v ss q dq3 v ss nf, dq5 v ss v dd zq0 v ref c a ba1 a4 a 6 a8 9 v dd v ddq v ss q v ss q v ddq c ke1 c ke0 zq1 v ss v dd v ss v dd v ss 1 v ss v ss v ddq v ss q v refdq odt1 odt0 cs 1# v ss v dd v ss v dd v ss a b c d e f g h j k l m n
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 5 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram ball assignments and descriptions table 3: 82-ball and 78-ball fbga ball descriptions symbol type description a14, a13, a12/bc#, a11, a10/ap, a[9:0] input address inputs: provide the row address for activate commands, and the column address and auto precharge bit (a10) for read/w rite commands, to sele ct one location out of the memory array in the respective ba nk. a10 sampled during a precharge command determines whether the prechar ge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to v refca . a12/bc#: wh en enabled in the mode register (mr), a12 is sampled during read and write commands to determine whether burst chop (on-the-fly) will be performed (high = burst length (bl) of 8 or no burst chop, low = burst chop (bc) of 4, burst chop). ba[2:0] input bank address inputs: ba[2:0] define the bank to which an activate, read, write, or precharge command is being ap plied. ba[2:0] defi ne which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ba[2:0] are referenced to v refca . ck, ck# input clock: ck and ck# are differential clock inputs. all control, command, and address input signals are sampled on the crossing of the posi tive edge of ck and the negative edge of ck#. output data strobe (dqs, dqs#) is re ferenced to the crossings of ck and ck#. cke[1:0] input clock enable: cke enables (registered high) and di sables (registered low) internal circuitry and clocks on the dram. the specific circuitr y that is enabled/disabled is dependent upon the ddr3 sdram configuration and operating mode. taking cke low provides precharge power-down and self refr esh operations (all banks idle) or active power-down (row active in an y bank). cke is synchronous for power-down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. in put buffers (excluding ck, ck#, cke, reset#, and odt) are disabled during power-down. input buffers (excluding cke and reset#) are disabled during se lf refresh. cke is referenced to v refca . cs#[1:0] input chip select: cs# enables (registered low) and di sables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external rank selection on systems with multiple ranks. cs# is considered part of the command code. cs# is referenced to v refca . dm input input data mask: dm is an input mask signal for wr ite data. input data is masked when dm is sampled high, along with the input da ta, during a write acce ss. although the dm ball is input-only, the dm loading is designed to match that of the dq and dqs balls. dm is referenced to v refdq . dm has an optional use as tdqs on the x8. odt[1:0] input on-die termination: odt enables (registered high) an d disables (registered low) termination resistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to each of the following ba lls: dq[7:0], dqs, dqs#, and dm for the x8; dq[3:0], dqs, dqs#, and dm fo r the x4. the odt input is ignored if disabled via the load mode command. odt is referenced to v refca . ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v refca . reset# input reset: reset# is an ac tive low cmos inpu t referenced to v ss . the reset# input receiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v ddq and dc low 0.2 v ddq . reset# assertion and de sertion are asynchronous. dq[3:0] i/o data input/output: bidirectional data bus for the x4 configuration. dq[3:0] are referenced to v refdq . dq[7:0] i/o data input/output: bidirectional data bus for the x8 configuration. dq[7:0] are referenced to v refdq . dqs, dqs# i/o data strobe: dqs and dqs# are differential data st robes. output with read data. edge- aligned with read data. input with write data. center-aligned with write data. tdqs, tdqs# output termination data strobe: applies to the x8 configuration only. when tdqs is enabled, dm is disabled, and the tdqs and tdqs # balls provide termination resistance. v dd supply power supply: 1.5v 0.075v.
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 6 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram ball assignments and descriptions v ddq supply dq power supply: 1.5v 0.075v. isolated on the de vice for improved noise immunity. v refca supply reference voltage for control, command, and address: v refca must be maintained at all times (including self refresh ) for proper device operation. v refdq supply reference voltage for data: v refdq must be maintained at all times (including self refresh) for proper device operation. v ss supply ground. v ssq supply dq ground: isolated on the device for improved noise immunity. zq[1:0] reference external reference ball for output drive calibration: this ball is tied to an external 240 resistor (rzq), wh ich is tied to v ssq . nc ? no connect: these balls should be left unconnecte d (the ball has no connection to the dram or to other balls). nf ? no function: when configured as a x4 device, these balls are nf. when configured as a x8 device, these balls are defined as tdqs#, dq[7:4]. table 3: 82-ball and 78-ball fbga ball descriptions (continued) symbol type description
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 7 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram functional description functional description the 4gb (twindie) ddr3 sdram is a high-speed, cmos dynamic random access mem- ory device containing 4,294,967,296 bits and is internally configured as two 8-bank 2gb ddr3 sdram. although each die is tested individually within the dual-die package, some twindie test results may vary from a like-die tested within a monolithic die package. the ddr3 sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cy cle at the i/o balls. a single read or write access consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o balls. the differential data strobes (dqs, dqs#) are transmitted externally, along with data, for use in data capture at the ddr3 sdram input receiver. dqs is center-aligned with data for writes. the read data is transmitted by the ddr3 sdram and edge-aligned to the data strobes. read and write accesses to the ddr3 sdra m are burst oriented. accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. the address bits (including cs n #, ba n , and a n ) registered coincident with the read or write com- mand are used to select the rank, bank, and starting column location for the burst access. this data sheet provides a general descri ption, package dimensions, and the package ballout. refer to the micron 2gb ddr3 data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die opera- tion.
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 8 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram functional block diagrams functional block diagrams figure 3: functional block diag ram (64 meg x 4 x 8 banks x 2 ranks) figure 4: functional block diag ram (32 meg x 8 x 8 banks x 2 ranks) ra s # c a s # we# re s et# c k c k# dq[3:0] dq s , dq s # dm a[14:0], ba[2:0] cs 0# c ke0 odt0 rank 0 ( 6 4 me g x 4 x 8 b anks) rank 1 ( 6 4 me g x 4 x 8 b anks) cs 1# c ke1 odt1 zq1 zq0 tdq s # c a s # ra s # we# c k c k# dq[7:0] dq s , dq s # dm/tdq s a[14:0], ba[2:0] rank 0 (32 me g x 8 x 8 b anks) rank 1 (32 me g x 8 x 8 b anks) cs 0# c ke0 odt0 zq0 cs 1# c ke1 odt1 zq1 re s et#
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 9 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram electrical specifications electrical specifications stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the device data sh eet is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. notes: 1. v dd and v ddq must be within 300mv of eac h other at all times, and v ref must not be greater than 0.6 v ddq . when v dd and v ddq are less than 500mv, v ref may be 300mv. 2. the minimum limit requirement is for testi ng purposes. the leakage current on the v ref pin should be minimal. 3. max operating case temperature. t c is measured in the center of the package (see figure 5 on page 10). 4. device functionality is not guaranteed if the dram device exceeds the maximum t c dur- ing operation. temperature and thermal impedance it is imperative that the ddr3 sdram devi ce?s temperature specifications, shown in table 5 on page 10, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specificat ions. an important step in maintaining the proper junction temperature is using the device?s thermal impedances correctly. ther- mal impedances listed in table 6 on page 10 apply to the current die revision and pack- ages. incorrectly using thermal impedances can produce significant errors. read micron tech- nical note tn-00-08: ?thermal applications,? prior to using the thermal impedances in table 6. for designs that are expected to last several years and require the flexibility to use several dram die shrinks, consider using final target theta values (rather than exist- ing values) to account for increased thermal impedances from the re duction in die size. the ddr3 sdram device?s safe junction temperature range can be maintained when the t c specification is not exceeded. in applic ations where the device?s ambient temper- ature is too high, use of forced air and/or he at sinks may be required to satisfy the case temperature specifications. table 4: absolute maximum ratings symbol parameter min max units notes v dd v dd supply voltage relative to v ss ?0.4 1.975 v 1 v ddq v dd supply voltage relative to v ssq ?0.4 1.975 v v in , v out voltage on any ball relative to v ss ?0.4 1.975 v i i input leakage current any input 0v v in v dd , v ref pin 0v v in 1.1v (all other pins not under test = 0v) ?4 +4 a i vref v ref supply leakage current v refdq = v dd /2 or v refca = v dd /2 (all other pins not under test = 0v) ?2 +2 a 2 t c operating case temperature 095c3, 4 t stg storage temperature ?55 150 c
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 10 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram electrical specifications notes: 1. max operating case temperature. t c is measured in the center of the package (see figure 5). 2. a thermal solution must be de signed to ensure the dram de vice does not exceed the max- imum t c during operation. 3. device functionality is no t guaranteed if the dram device exceeds the maximum t c during operation. 4. if t c exceeds 85c, the dram must be refreshed externally at 2x refresh, which is a 3.9s interval refresh rate. the use of self refresh temperature (srt) or automatic self refresh (asr), if available, must be enabled. notes: 1. thermal resistance data is based upon a nu mber of samples from multiple lots and should be viewed as a typical number. figure 5: temperature test point location table 5: thermal characteristics parameter/condition symbol value units notes operating case temperature t c 0 to 85 c 1, 2, 3 0 to 95 c 1, 2, 3, 4 table 6: thermal impedance die rev package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) notes a 82-ball 2-layer 46.0 33.9 28.1 25.6 1.73 1 4-layer 34.2 27.1 23.6 23.2 d 78-ball 2-layer 61.0 43.7 37.3 27.1 2.8 1 4-layer 44.5 35.3 31.5 23.2 test point length (l) width (w) 0.5 (w) 0.5 (l)
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 11 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram electrical specifications i dd specifications and conditions notes: 1. i cdd values reflect the co mbined current of both individual die. i dd x represents individual die value s . ta bl e 7 : dd r3 i cdd specifications and conditions ? rev. a note 1 applies to the entire table. combined symbol individual die status width -25/ -25e -187/ -187e -15/ -15e units i cdd0 i cdd0 = i dd0 + i dd2p0 + 5 x4 92 107 117 ma x8 117 137 147 ma i cdd1 i cdd1 = i dd1 + i dd2p0 + 5 x4 117 132 147 ma x8 132 152 172 ma i cdd2p0 (slow exit) i cdd2p0 = i dd2p0 + i dd2p0 x4/x8242424ma i cdd2p1 (fast exit) i cdd2p1 = i dd2p1 + i dd2p0 42 47 52 ma i cdd2q i cdd2q = i dd2q + i dd2p0 x4/x8677787ma i cdd2n i cdd2n = i dd2n + i dd2p0 x4/x8728292ma i cdd2nt i cdd2nt = i dd2nt + i dd2p0 77 87 97 ma i cdd3p i cdd3p = i dd3p + i dd2p0 x4/x8626777ma i cdd3n i cdd3n = i dd3n + i dd2p0 x4/x8 82 92 107 ma i cdd4w i cdd4w = i dd4w + i dd2p0 + 5 x4 212 242 272 ma x8 277 312 347 ma i cdd4r i cdd4r = i dd4r + i dd2p0 + 5 x4 192 217 247 ma x8 212 242 272 ma i cdd5b i cdd5b = i dd5b + i dd2p0 x4/x8 287 302 317 ma i cdd6 i cdd6 = i dd6 + i dd6 x4/x8202020ma i cdd6et i cdd6et = i dd6et + i dd6et x4/x8282828ma i cdd7 i cdd7 = i dd7 + i dd2p0 + 5 x4 337 362 432 ma x8 417 447 477 ma i cdd8 i cdd8 = 2 i dd2p0 + 4 all 28 28 28 ma
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 12 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram electrical specifications notes: 1. i cdd values reflect the co mbined current of both individual die. i dd x represents individual die value s . ta bl e 8 : dd r3 i cdd specifications and conditions ? rev. d note 1 applies to the entire table. combined symbol individual die status width -187/ -187e -15/ -15e units i cdd0 i cdd0 = i dd0 + i dd2p0 + 5 x4 82 87 ma x8 82 87 ma i cdd1 i cdd1 = i dd1 + i dd2p0 + 5 x4 102 107 ma x8 102 107 ma i cdd2p0 (slow exit) i cdd2p0 = i dd2p0 + i dd2p0 x4/x8 24 24 ma i cdd2p1 (fast exit) i cdd2p1 = i dd2p1 + i dd2p0 32 37 ma i cdd2q i cdd2q = i dd2q + i dd2p0 x4/x8 42 47 ma i cdd2n i cdd2n = i dd2n + i dd2p0 x4/x8 44 49 ma i cdd2nt i cdd2nt = i dd2nt + i dd2p0 52 57 ma i cdd3p i cdd3p = i dd3p + i dd2p0 x4/x8 42 47 ma i cdd3n i cdd3n = i dd3n + i dd2p0 x4/x8 47 52 ma i cdd4w i cdd4w = i dd4w + i dd2p0 + 5 x4 147 167 ma x8 147 167 ma i cdd4r i cdd4r = i dd4r + i dd2p0 + 5 x4 142 162 ma x8 142 162 ma i cdd5b i cdd5b = i dd5b + i dd2p0 x4/x8 202 217 ma i cdd6 i cdd6 = i dd6 + i dd6 x4/x8 24 24 ma i cdd6et i cdd6et = i dd6et + i dd6et x4/x8 30 30 ma i cdd7 i cdd7 = i dd7 + i dd2p0 + 5 x4 287 337 ma x8 287 337 ma i cdd8 i cdd8 = 2 i dd2p0 + 4 all 28 28 ma
pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 13 ?2008 micron technology, inc. all rights reserved. 4gb: x4, x8 twindie ddr3 sdram package dimensions package dimensions figure 6: 82-ball fbga package dimensions ? rev. a note: all dimensions are in millimeters. ball a1 id 1 0.05 seating plane 0.1 a a 1.35 max 0.8 typ 0.8 typ 4 8 12.5 0.1 6.25 0.05 82x ?0.45 solder ball material: 96.5% sn, 3% ag, 0.5% cu mold compound: epoxy novolac substrate material: plastic laminate 9.6 4.8 7.5 0.05 15 0.1 ball a1 id dimensions apply to solder balls post-reflow. pre- reflow ball is ?0.42 on a ?0.33 nsmd ball pad. 11 10 9 8 4 3 2 1 a b c d e f g h j k l m n
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron, the micron logo, and twindie are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 4gb: x4, x8 twindie ddr3 sdram package dimensions pdf: 09005aef83188bab/source: 09005aef83169de6 micron technology, inc., reserves the right to change products or specifications without notice. mt41j1g4_64m_32m_twindie.fm - rev. f 11/09 en 14 ?2008 micron technology, inc. all rights reserved. figure 7: 78-ball fbga package dimensions ? rev. d note: all dimensions are in millimeters. ball a1 id seating plane 0.12 a a 0.8 0.1 1.2 max 0.25 min 9 0.15 ball a1 id 9.6 ctr solder ball material: sac305. dimensions apply to solder balls post- reflow on ?0.35 smd ball pads. 78x ?0.45 11.5 0.15 0.8 typ 0.8 typ 6.4 ctr 9 8 7 3 2 1 a b c d e f g h j k l m n

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